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In the computer system, because of the increasing of the scale and performance, conventinal development can not maintain the quality of software. Also, if it problems occur with important software, it becomes a big social problem.
For this reason, the quality of software is emphasized than before.
It is possible to eliminate ambiguity and bliefs early in the software development by creating software specification strictly with not natral languages but formal specification languages that is based on mathmatical logic. Also it's possible to increase the quality
And it is possible to deepen scientific and systematic analysis of the system, to reduce the cost by rework, and improve quality.
VDM (Vienna Development Method) is a one of the Formal Methods, and VDM-SL is a specification language of VDM.
Also, in the designing stage of software, Decision Table is widely known that is possible to express the logic of software.
This method can be used for software designing, organization of specification, and desiging of test cases.
To improve the efficiency of test designing in the development with formal methods, we implemented VDTable (VDM Decision Table) that generate a decision table automatically based on a specification written in VDM++.
input : the specification written in VDM++
output : a decision table
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To improve the practicality of VDTable.
In particular, it corresponds to the compound conditional expressions.
When there is compound conditional expressions that are combine two or more conditional expressions, by using logical operators (ex. 'and', 'or', 'not'), VDTable extract its expressions without devide into the simple conditinal expressions.
appearance of current VDTable
We impelement the function to DT0Generator to be possible to devide the compound conditional expressions into simple expressions.
Scheduled output after implementation
E-mail : hm12056@student.miyazaki-u.ac.jp
Last Updated : 2017/02/28
By Kou Itsudaku